Conformal, uniform dielectric films have many applications in semiconductor manufacturing. In the fabrication of sub-micron integrated circuits (ICs) several layers of dielectric film are deposited. Four such layers are shallow trench isolation (STI), pre-metal dielectric (PMD), inter-metal dielectric (IMD) and inter-layer dielectric (ILD). Other applications of conformal dielectric films may be as passivation layers, sacrificial or permanent spacer layers, sacrificial or permanent storage node separation layers, or as dielectric liners for through-wafer vias. These layers require silicon dioxide or other dielectric films that fill features of various sizes and have high conformality and uniform film thicknesses across the substrate.
Additionally, challenges associated with shrinking device footprints, increased interconnections, and higher thermal and power loads have created an opportunity for through-wafer vias. New wafer-level packaging technology has evolved from conventional IC interconnect fabrication to the use of through-wafer vias in three-dimensional (3-D) stacked chip packages. Previously, most stacked devices were interconnected by wire bonding at the periphery of the chips. Now, through-wafer vias serve as an electrical connection between stacked chips, analogous to the role of electrical interconnects within an IC. In most embodiments, deep vias are etched through the Si substrate of each device, lined with an insulating material, coated with a diffusion barrier, and filled with a conducting metal. The vias have diameters of approximately 100 um or less and depths of up to 700 um, resulting in high-aspect ratio features that require a highly conformal dielectric film to form a continuous insulating liner in the via.
Other recent and developing applications for conformal, uniform dielectric films are as sacrificial layers in various steps of IC fabrication. A sacrificial layer may be used as a mask for subsequent etching and/or deposition steps, for which a highly uniform film is required. Sacrificial layers may also serve as structural materials during IC fabrication, to be removed following particular processing steps. These applications may require specific film properties relating to conformality, within-wafer uniformity, wet etch rate, mechanical strength, hardness, dielectric constant, leakage, and breakdown field.
In some applications, the dielectric deposition must take place on a substrate also comprising temperature-sensitive materials with reduced thermal budgets. In that case, the surface preparation, dielectric deposition, and post-deposition treatments must occur at maximum temperatures that may not exceed approximately 200 degrees Celsius, and less than about 100 degrees Celsius in some embodiments.
Chemical vapor deposition (CVD) has traditionally been the method of choice for depositing silicon dioxide films. However, as design rules continue to shrink, the aspect ratios (depth to width) of features increase, and traditional CVD techniques can no longer provide void-free gap-fill in these high aspect ratio features.
An alternative to CVD is atomic layer deposition (ALD). ALD methods involve cycling of self-limiting adsorption/reaction steps of reactant gases and can provide thin, conformal films within high aspect ratio features. The ALD process involves exposing a substrate to alternating doses of, usually two, reactant gases. As an example, if reactants A and B are first and second reactant gases for an ALD process, after A is adsorbed onto the substrate surface to form a saturated layer, B is introduced and reacts only with adsorbed A. In this manner, a very thin and conformal film can be deposited. One drawback, however, to ALD is that the deposition rates are very low. Films produced by an ALD cycle are very thin (i.e., about one monolayer); therefore, numerous ALD cycles must be repeated to adequately fill a gap feature. These processes are unacceptably slow in some applications in the manufacturing environment.
Another more recently developed technique useful in dielectric gap fill and other deposition applications in semiconductor processing is referred to as pulsed deposition layer (PDL) processing, sometimes also referred to as surface-catalyzed rapid vapor deposition (RVD). PDL is similar to ALD in that reactant gases are introduced alternately over the substrate surface, but in PDL the first reactant A acts as a catalyst, promoting the conversion of the second reactant B to a film. In ALD the reaction between A and B is approximately stoichiometric, meaning that a monolayer of A can only react with a similar amount of B before the film-forming reaction is complete. The catalytic nature of A in PDL allows a larger amount of B to be reacted, resulting in a thicker film that is much greater than one monolayer. Typically, up to 120 angstroms of film may be deposited in one iteration of the PDL process. Thus, PDL methods allow for faster film growth with similar film conformality to ALD methods.